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<div class="header">
  <div class="headertitle"><div class="title">I2C_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>Inter-integrated Circuit Interface.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:a91782f7b81475b0e3c3779273abd26aa" id="r_a91782f7b81475b0e3c3779273abd26aa"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a91782f7b81475b0e3c3779273abd26aa">CR1</a></td></tr>
<tr class="memitem:a29eb47db03d5ad7e9b399f8895f1768c" id="r_a29eb47db03d5ad7e9b399f8895f1768c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a29eb47db03d5ad7e9b399f8895f1768c">CR2</a></td></tr>
<tr class="memitem:ae8269169fcbdc2ecb580208d99c2f89f" id="r_ae8269169fcbdc2ecb580208d99c2f89f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae8269169fcbdc2ecb580208d99c2f89f">OAR1</a></td></tr>
<tr class="memitem:a73988a218be320999c74a641b3d6e3c1" id="r_a73988a218be320999c74a641b3d6e3c1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a73988a218be320999c74a641b3d6e3c1">OAR2</a></td></tr>
<tr class="memitem:a92514ade6721d7c8e35d95c5b5810852" id="r_a92514ade6721d7c8e35d95c5b5810852"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a92514ade6721d7c8e35d95c5b5810852">TIMINGR</a></td></tr>
<tr class="memitem:a95f1607b6254092066a3b6e35146e28a" id="r_a95f1607b6254092066a3b6e35146e28a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a95f1607b6254092066a3b6e35146e28a">TIMEOUTR</a></td></tr>
<tr class="memitem:a0f73f2b049d95841c54313f0cc949afe" id="r_a0f73f2b049d95841c54313f0cc949afe"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0f73f2b049d95841c54313f0cc949afe">ISR</a></td></tr>
<tr class="memitem:a790a1957ec69244915a9637f7d925cf7" id="r_a790a1957ec69244915a9637f7d925cf7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a790a1957ec69244915a9637f7d925cf7">ICR</a></td></tr>
<tr class="memitem:a64c9036c1b58778cda97efa2e8a4be97" id="r_a64c9036c1b58778cda97efa2e8a4be97"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a64c9036c1b58778cda97efa2e8a4be97">PECR</a></td></tr>
<tr class="memitem:a43d30d8efd8e4606663c7cb8d2565e12" id="r_a43d30d8efd8e4606663c7cb8d2565e12"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a43d30d8efd8e4606663c7cb8d2565e12">RXDR</a></td></tr>
<tr class="memitem:ad243ba45c86b31cb271ccfc09c920628" id="r_ad243ba45c86b31cb271ccfc09c920628"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ad243ba45c86b31cb271ccfc09c920628">TXDR</a></td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Inter-integrated Circuit Interface. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="a91782f7b81475b0e3c3779273abd26aa" name="a91782f7b81475b0e3c3779273abd26aa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a91782f7b81475b0e3c3779273abd26aa">&#9670;&#160;</a></span>CR1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t I2C_TypeDef::CR1</td>
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<p>I2C Control register 1, Address offset: 0x00 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a29eb47db03d5ad7e9b399f8895f1768c">&#9670;&#160;</a></span>CR2</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t I2C_TypeDef::CR2</td>
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<p>I2C Control register 2, Address offset: 0x04 </p>

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<a id="a790a1957ec69244915a9637f7d925cf7" name="a790a1957ec69244915a9637f7d925cf7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a790a1957ec69244915a9637f7d925cf7">&#9670;&#160;</a></span>ICR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t I2C_TypeDef::ICR</td>
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<p>I2C Interrupt clear register, Address offset: 0x1C </p>

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<a id="a0f73f2b049d95841c54313f0cc949afe" name="a0f73f2b049d95841c54313f0cc949afe"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0f73f2b049d95841c54313f0cc949afe">&#9670;&#160;</a></span>ISR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t I2C_TypeDef::ISR</td>
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<p>I2C Interrupt and status register, Address offset: 0x18 </p>

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<a id="ae8269169fcbdc2ecb580208d99c2f89f" name="ae8269169fcbdc2ecb580208d99c2f89f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae8269169fcbdc2ecb580208d99c2f89f">&#9670;&#160;</a></span>OAR1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t I2C_TypeDef::OAR1</td>
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<p>I2C Own address 1 register, Address offset: 0x08 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a73988a218be320999c74a641b3d6e3c1">&#9670;&#160;</a></span>OAR2</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t I2C_TypeDef::OAR2</td>
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<p>I2C Own address 2 register, Address offset: 0x0C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a64c9036c1b58778cda97efa2e8a4be97">&#9670;&#160;</a></span>PECR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t I2C_TypeDef::PECR</td>
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<p>I2C PEC register, Address offset: 0x20 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a43d30d8efd8e4606663c7cb8d2565e12">&#9670;&#160;</a></span>RXDR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t I2C_TypeDef::RXDR</td>
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<p>I2C Receive data register, Address offset: 0x24 </p>

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<a id="a95f1607b6254092066a3b6e35146e28a" name="a95f1607b6254092066a3b6e35146e28a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a95f1607b6254092066a3b6e35146e28a">&#9670;&#160;</a></span>TIMEOUTR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t I2C_TypeDef::TIMEOUTR</td>
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<p>I2C Timeout register, Address offset: 0x14 </p>

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<a id="a92514ade6721d7c8e35d95c5b5810852" name="a92514ade6721d7c8e35d95c5b5810852"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a92514ade6721d7c8e35d95c5b5810852">&#9670;&#160;</a></span>TIMINGR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t I2C_TypeDef::TIMINGR</td>
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<p>I2C Timing register, Address offset: 0x10 </p>

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<a id="ad243ba45c86b31cb271ccfc09c920628" name="ad243ba45c86b31cb271ccfc09c920628"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad243ba45c86b31cb271ccfc09c920628">&#9670;&#160;</a></span>TXDR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t I2C_TypeDef::TXDR</td>
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<p>I2C Transmit data register, Address offset: 0x28 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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